Understanding the M.2 Slot: Theoretical Bandwidth vs Actual Speed

Question:

How is the theoretical bandwidth of an M.2 slot calculated and why is it much higher than the actual speed achieved by PCIe 3?

I am curious about the relationship between the theoretical bandwidth and the actual speed of an M.2 slot on my motherboard. The specification claims that the M.2 slot can reach up to 32GB/s, but since my motherboard only supports PCIe 3, the maximum speed I can get is around 3.5GB/s – 4GB/s. How is the 32GB/s figure derived and what factors limit the real-world performance of the M.2 slot?

Answer:

How is the theoretical bandwidth of an M.2 slot calculated and why is it much higher than the actual speed achieved by PCIe 3?

M.2 is a form factor for storage devices that can connect to the motherboard via different interfaces, such as SATA, PCIe, or NVMe. The theoretical bandwidth of an M.2 slot depends on the interface and the number of lanes it uses. PCIe, or Peripheral Component Interconnect Express, is a high-speed serial bus that can transfer data between the CPU and other components, such as graphics cards, sound cards, or storage devices. PCIe has different generations, each with a different transfer rate per lane. A lane is a pair of differential signal wires, one for sending and one for receiving. PCIe devices can use multiple lanes to increase the bandwidth, up to 16 lanes for some graphics cards.

The theoretical bandwidth of a PCIe device is calculated by multiplying the transfer rate per lane by the number of lanes. For example, PCIe 3.0 has a transfer rate of 8 GT/s (gigatransfers per second) per lane, which means it can transfer 8 billion bits per second. However, due to encoding overhead, the effective data rate is reduced to 7.877 Gb/s (gigabits per second) per lane. Therefore, a PCIe 3.0 device that uses 4 lanes (x4) has a theoretical bandwidth of 7.877 Gb/s x 4 = 31.508 Gb/s, or approximately 32 GB/s (gigabytes per second).

However, the actual speed achieved by a PCIe device is often lower than the theoretical bandwidth, due to various factors, such as:

  • Protocol overhead: PCIe uses a packet-based protocol, which means that data is divided into smaller units called packets, each with a header and a footer that contain information such as the source, destination, and error correction. These headers and footers add extra bits that reduce the effective data rate. For example, a PCIe 3.0 packet has a 20-byte header and a 4-byte footer, which means that for every 32 bytes of data, there are 24 bytes of overhead, or a 25% reduction in data rate.
  • Latency: Latency is the delay between the time a request is sent and the time a response is received. Latency can be affected by the distance between the components, the quality of the signal, the number of hops or switches, and the congestion or contention on the bus. Latency can reduce the throughput, or the amount of data transferred per unit of time, especially for small or random requests that require frequent communication.
  • Device limitations: The speed of a PCIe device also depends on the performance and capabilities of the device itself, such as the controller, the flash memory, the cache, or the firmware. For example, some M.2 SSDs may have a slower controller or lower-quality flash memory that limit their read and write speeds. Some M.2 SSDs may also have a thermal throttling mechanism that reduces their speed when they overheat.
  • Motherboard limitations: The speed of a PCIe device also depends on the configuration and compatibility of the motherboard, such as the chipset, the BIOS, or the drivers. For example, some motherboards may not support the full potential of the PCIe interface or the M.2 slot, or may have shared bandwidth with other components that cause bottlenecks. Some motherboards may also have outdated BIOS or drivers that need to be updated to enable the optimal performance of the PCIe device.
  • In

conclusion, the theoretical bandwidth of an M.2 slot is calculated by multiplying the transfer rate per lane by the number of lanes, depending on the interface and the generation of the PCIe bus. However, the actual speed achieved by a PCIe device is often lower than the theoretical bandwidth, due to various factors, such as protocol overhead, latency, device limitations, and motherboard limitations. Therefore, it is important to check the specifications and reviews of both the M.2 device and the motherboard before purchasing or installing them, to ensure the best compatibility and performance.

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